The present invention relates to a solid state imaging device having a plurality of light receiving pixels arranged in a matrix-like manner and a method for driving such solid state imaging device.
In an imaging device, such as a digital camera, a preview of a captured image is shown as a dynamic image. The resolution of a preview does not have to be as high as a still image. Thus, image signals, which are output from a solid state imaging device, are thinned out to generate the dynamic image.
FIG. 1 is a schematic circuit block diagram of a prior art imaging device 50. FIG. 2 is a timing chart illustrating the horizontal transfer and output operation of the imaging device 50. FIG. 1 shows a solid state imaging device 1 having a matrix formed by six rows and eight columns. The solid state imaging device 1 has a light receiving portion for generating information charges. An output section 1d of the solid state imaging device 1 synthesizes a predetermined amount of the information charges to thin out the image signals.
The solid state imaging device 1 is, for example, a frame transfer type device. The solid state imaging device 1 includes a light receiving portion 1i for receiving a captured image and generating information charges, a storage portion 1s for temporarily storing the generated information charges, a horizontal shift register 1h for transferring the information charges in the row (horizontal) direction, and the output section 1d for converting the information charges to a voltage having a value that is in accordance with the charge amount of the information charges.
The drive circuit 2 includes a frame transfer clock generation circuit 2f, a vertical transfer clock generation circuit 2v, a horizontal clock generation circuit 2h, a reset clock generation circuit 2r, a sampling clock generation circuit 2s, and a substrate clock generation circuit 2b. 
In response to a frame transfer timing signal FT, the frame transfer clock generation circuit 2f generates, for example, a frame transfer clock "PHgr"f having four phases and provides the frame transfer clock "PHgr"f to the light receiving portion 1i. Information charges for a single screen image, which are accumulated in light receiving pixels of the light receiving portion 1i, are transferred to the storage portion 1s in accordance with the frame transfer clock "PHgr"f and in synchronism with a vertical scanning period.
In response to a vertical synchronizing signal VT and a horizontal synchronizing signal HT, the vertical transfer clock generation circuit 2v generates, for example, a vertical transfer clock "PHgr"v having four phase and provides the vertical transfer clock "PHgr"v to the storage portion 1s. The information charges received from the light receiving portion 1i are temporarily accumulated in the storage portion 1s in accordance with the vertical transfer clock "PHgr"v and in synchronism with a frame transfer timing. The accumulated information charges are provided to the horizontal shift register 1h in units of rows for each horizontal scanning period 1H.
In response to the horizontal synchronizing signal HT, the horizontal transfer clock generation circuit 2h generates, for example, a transfer clock "PHgr"h having two phases and provides the frame transfer clock "PHgr"h to the horizontal shift register 1h. The information charges corresponding to a single row, which is received in each bit register of the horizontal shift register 1h, is provided to the output section id sequentially in units of single pixels.
The reset clock generation circuit 2r generates a reset clock "PHgr"r in synchronism with the horizontal transfer clock generation circuit 2h and provides the reset clock "PHgr"r to the output section 1d. The information charges transferred from the horizontal shift register 1h in units of single pixels are converted to a voltage having a value that is in accordance with the charge amount in response to the reset clock "PHgr"r and sequentially output.
In the same manner as the reset clock generation circuit 2r, the sampling clock generation circuit 2s generates the sampling clock "PHgr"s in synchronism with the operation of the horizontal transfer clock generation circuit 2h and provides the sampling clock "PHgr"s to the sample hold circuit 4. In accordance with the sampling clock "PHgr"s and in synchronism with the horizontal scanning period, among the reset level and the signal level, which are repeated in an image signal Y0(t), only the signal level is extracted to generate an image signal Y1(t) having consecutive signal levels.
In response to a drain timing signal BT, the substrate clock generation circuit 2b generates a substrate clock "PHgr"b that disposes of information charges accumulated in the light receiving portion 1i and provides the substrate clock "PHgr"b to a substrate side of the solid state imaging device 1.
The timing control circuit operates in accordance with a reference clock CK having a constant cycle. The timing control circuit 3 generates the vertical synchronizing signal VT and the horizontal synchronizing signal HT, which determine the vertical and horizontal scanning timing of the solid state imaging device 1, and generates a frame transfer timing signal FT at a cycle coinciding with the vertical synchronizing signal VT. The timing control circuit 3 generates the drain timing signal BT in accordance with integral data that represents the integral value of a single screen image provided from a digital signal processing circuit (not shown) or the integral value of an arbitrary section.
The drain timing signal BT is provided to the drive circuit 2 together with the vertical synchronizing signal VT, the horizontal synchronizing signal HT, and the frame transfer timing signal FT. The drain timing signal BT delays the drain timing when the integral data exceeds a value that is adequate for shortening the storage time of the information charges. On the other hand, the drain timing signal BT advances the drain timing when the integral value becomes smaller than the adequate value to lengthen the storage time. To optimize the exposure state of the solid state imaging device 1, feedback control is performed in accordance with the drain timing signal BT.
A dividing circuit 5 includes a first divider 5a for dividing the sampling clock "PHgr"s and a second divider 5b for dividing the reset clock "PHgr"r. The dividing circuit 5 divides the reset clock "PHgr"r and the sampling clock "PHgr"s when necessary. The output section 1d is operated intermittently in accordance with the divided reset clock "PHgr"r and the divided sampling clock "PHgr"s to mix information charges.
For example, when the cycle of the reset clock "PHgr"r, the cycle of which is the same as that of the horizontal transfer clock "PHgr"h, is divided by xc2xd, a reset clock "PHgr"rxe2x80x2 having a cycle that is two times longer is generated. The reset clock "PHgr"rxe2x80x2 resets the information charges whenever information charges for two pixels are accumulated in the output section 1d. This synthesizes the information charges for two pixels, which are arranged adjacent to each other in the horizontal direction, and thins out the information charges.
In the prior art imaging device 50, a color filter is attached to the light receiving portion 1i when performing color imaging. The color filter includes a plurality of different segments corresponding to the three primary colors and their auxiliary colors. The segments are arranged in a two dimensional manner and correspond in a regular manner with each light receiving pixel. In the color imaging solid state imaging device 1 that associates certain color components with each light receiving pixel, the color components of the light receiving pixels adjacent to each other in the horizontal direction are different. Thus, the information charges of pixels in the horizontal direction cannot be synthesized.
For example, when using a mosaic color filter having three color components R (red), G, (green), and B (blue), referring to FIG. 2, the generated image signal Y0(t) has the color components R and G, which are alternately repeated in synchronism with the horizontal transfer clock "PHgr"h, or the color components B and G, which are also alternately repeated in synchronism with the horizontal transfer clock "PHgr"h. Thus, when the information charges of adjacent light receiving pixels are synthesized in a transfer stage, different color components are mixed together. Thus, the desired color cannot be obtained at the reproducing side.
It is an object of the present invention to provide a solid state imaging device that optimally thins out information charges in the horizontal direction even during color imaging.
To achieve the above object, the present invention provides a solid state imaging device including a light receiving section including a plurality of light receiving pixels. The light receiving pixels are arranged in rows and columns in a matrix-like manner and accumulate information charges. A plurality of vertical shift registers are connected to the light receiving section for transferring the information charges accumulated in the light receiving pixels in a vertical direction. A horizontal shift register is connected to the vertical shift registers and includes a plurality of bit regions. The bit regions receive information charges transferred from the vertical shift registers, and the horizontal shift register transfers the information charges accumulated in the light receiving pixels in a horizontal direction at a ratio of m/n (m, n both being natural numbers and satisfying m less than n). An output section is connected to an output of the horizontal shift register. The output section receives the information charges transferred in the horizontal direction and generates an image signal having a voltage corresponding to the charge amount of the information charges. A drain section is connected to the horizontal shift register for collecting the information charges received in the horizontal shift register. The drain section is connected to a kxc2x7(nxe2x88x92m) (k being a natural number) number of the bit regions in a kxc2x7n number of bit regions of the horizontal shift register, and the horizontal shift register transfers the information charges of the kxc2x7(nxe2x88x92m) number of the bit regions in the kxc2x7n number of bit regions to the drain section.
A further perspective of the present invention is a solid state imaging device including a light receiving section including a plurality of light receiving pixels. The light receiving pixels are arranged in rows and columns in a matrix-like manner and accumulate information charges. A plurality of vertical shift registers are connected to the light receiving section for transferring the information charges accumulated in the light receiving pixels in a vertical direction. A horizontal shift register is connected to the vertical shift registers and includes a plurality of bit regions. The bit regions receive information charges transferred from the vertical shift registers, and the horizontal shift register transfers the received information charges in a horizontal direction. An output section is connected to an output of the horizontal shift register. The output section receives the information charges transferred in the horizontal direction and generates an image signal having a voltage corresponding to the charge amount of the information charges. A drain section is connected to the horizontal shift register for collecting the information charges received in the horizontal shift register. The drain section is connected to some of the bit regions of the horizontal shift register. The horizontal shift register transfers the information charges of the some of the bit regions to the drain section and transfers the information charges of the remaining bit regions to the output section.
A further perspective of the present invention is a method for driving a solid state imaging device including a plurality of light receiving pixels. The light receiving pixels are arranged in rows and columns in a matrix-like manner and accumulate information charges. The solid state imaging device thins out the information charges in a horizontal direction at a ratio of m/n (m, n both being natural numbers and satisfying m less than n) and outputs the thinned out information charges. The solid state imaging device includes a plurality of vertical shift registers. A horizontal shift register has a plurality of bit regions connected to the vertical shift registers. An output section is connected to an output of the horizontal shift register, and a drain section is connected to a k(nxe2x88x92m) (k being a natural number) number of bit regions in a kxc2x7n number of the bit regions of the horizontal shift register. The method includes receiving the information charges accumulated in the light receiving pixels with the vertical shift registers, vertically transferring the information charges received in the vertical shift registers to the horizontal shift register in units of single rows, transferring the information charges of the kxc2x7(nxe2x88x92m) number of bit regions in the kxc2x7n number of the bit regions to the drain section, and horizontally transferring the information charges of a kxc2x7n number of the bit regions in the kxc2x7n number of the bit regions to the output section.
A further perspective of the present invention is a method for driving a solid state imaging device including a plurality of light receiving pixels. The light receiving pixels are arranged in rows and columns in a matrix-like manner and accumulate information charges. The solid state imaging device thins out the information charges in a horizontal direction at a predetermined ratio. The solid state imaging device includes a plurality of vertical shift registers, a horizontal shift register having a plurality of bit regions connected to the vertical shift registers, an output section connected to an output of the horizontal shift register, and a drain section connected to some of the bit regions of the horizontal shift register. The method includes receiving the information charges accumulated in the light receiving pixels with the vertical shift registers, vertically transferring the information charges received in the vertical shift registers to the horizontal shift register in units of single rows, transferring the information charges of the some of the bit regions to the drain section, and horizontally transferring the information charges of remaining ones of the bit regions after excluding the some of the bit regions to the output section.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.